1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to the improvement of a signal input portion of an emitter-coupled logic (ECL) integrated circuit.
2 Description of the Related Art
The chip area of an advanced ECL integrated circuit is often increased, and therefore, some connection lines between a plurality of input signal pads and a plurality of input signal buffers such as address buffers become long. Consequently, if the distance between an input signal pad and an emitter follower transistor used as a signal input portion is large, for example, the input capacitance of an input signal is increased due to the parasitic capacitance of a long connection therebetween, thus increasing the access time.
To avoid this, in the prior art only the emitter follower transistor of the signal input portion is in proximity to the input signal pad, while a current source of the signal input portion is left on the circuit side of the input signal buffer, thereby reducing the input capacitance for an input signal. In this case, however, if the current flowing through the emitter follower is increased, the potential fall due to the resistance of signal paths is large so that the post input stage circuits may not operate normally. Contrary to this, if the current flowing through the emitter follower is decreased, the propagation speed of the input signal level becomes large due to the parasitic capacitance, thereby reducing the access time. Thus, in this case, it is impossible to satisfy the two conditions regarding the potential fall and the propagation speed of the signal level.